The interface to 8-bit ISA card for my C-Z80 Computer is now ready. I`ve addes some additional jumpers for setting address pins A16-A19 on the ISA bus and terminating the AEN signal (grounding it). There are also other ISA signals routed to pinheaders for any possible future uses. The interface is theoreticaly capable of handling CGA card (haven`t tested it yet), for which I`ve also added an 14 Mhz generator connected to “OSC” pin on the ISA bus (I`ve checked that my CGA card does not boot in a PC, when this signal is disconnected, so it`s probably necessary). At this moment I`m using a “MAGIC COMBO” MDA/Hercules/CGA card, which can be jumper-switched to operate as CGA or MDA/Hercules and it also can output either to Hercules mono or RGB color monitor. This latter feature is very interesting, as it is very easy to interface it with regular TV set with SCART connector. The card offers one parallel printer interface as a bonus. From the Z80 side, The ISA card is seen trough three I/O addresses:
- ffe0h – Video memory buffer (read / write)
- ffe1h – I/0 access (read / write)
- ffe2h – Low address latch (A0-A7) (write only)
- ffe3h – High address latch (A8-A15) (write only)
Here is an example program. It initializes the card to MDA mode, clears the screen and displays a nice looking ASCII art by Joan Stark ( http://www.oocities.org/spunk1111/indexjava.htm ).
;Some basic delay routines DELAY_LONG: .equ 0597h DELAY: .equ 0589h ; IO addresses and pin connections used: ; ffe0 - I/O address for memory write / read ; ffe1 - I/O address for port write / read ; ffe2 - write to low address register ; ffe3 - write to high address register ;Card`s IRQ7 - leave unconnected ;Some signals are terminated: ; ;A12,A13,A14,A15,A18,AEN = GND ;A16,A17,A19 = +5V ; ; *** MAIN LOOP *** .org 0d000h start: call port_setup call registers_init repeat: call clear_screen ld ix,test_string1 ld hl,0 call line_write jp 0000 ; *** SUBROUTINES *** port_setup: ; Seting up control port of 6845 CRT controller on MDA card (address 3b8h) ; According to "IBM Monochrome Display and Prnter Adapter" hardware reference manual ; this must be done before anything else. ; value "29h" means: ; High resolution mode: ON, Video Enable: ON, Enable Blink: ON ld bc,0ffe3h ld a,03h out (c),a ld bc,0ffe2h ld a,0b8h out (c),a ld bc,0ffe1h ld a,29h out (c),a ret registers_init: ; Bulk initialization of 6845 CRT controller`s registers ; 16 registers has to be initialised with fixed values ; recommended by IBM`s hadware manual for MDA card. ; Registers are selected by "Index Register" (3b4h) ; Values are entered to "Data Register" (3b5h) ld ix,init_data ld d,10h loop_regs: dec d ld a,(ix) ld e,a call reg_write inc ix ld a,0 cp d jr nz,loop_regs ret reg_write: ; writing value to 6845 register. ;Entry: ; ; D - register number ; E - value ld bc,0ffe3h ld a,03h out (c),a ld bc,0ffe2h ld a,0b4h out (c),a ld bc,0ffe1h ld a,d out (c),a ld bc,0ffe3h ld a,03h out (c),a ld bc,0ffe2h ld a,0b5h out (c),a ld bc,0ffe1h ld a,e out (c),a ret line_write: ;Write ASCIIZ buffer to MDA card`s video buffer. Assuming "normal" attribute. ;Entry: ; ; HL = Video RAM position - even address, counted from 0 ; IX = Start of ASCIIZ buffer of data ld bc,0ffe3h ld a,h out (c),a ld bc,0ffe2h ld a,l out (c),a ld b,0 ld a,(ix) cp b ret z ld bc,0ffe0h out (c),a inc hl ld bc,0ffe3h ld a,h out (c),a ld bc,0ffe2h ld a,l out (c),a ld bc,0ffe0h ld a,07h ;normal attribute out (c),a inc hl inc ix jp line_write clear_screen: ;Fills the 4K video RAM with zeros ld hl,0f9fh continue_clear_screen: ld bc,0ffe3h ld a,h out (c),a ld bc,0ffe2h ld a,l out (c),a ld bc,0ffe0h ld a,0 ;attribute out (c),a dec hl ld bc,0ffe3h ld a,h out (c),a ld bc,0ffe2h ld a,l out (c),a ld bc,0ffe0h ld a,0 ;empty char out (c),a ld a,h or l ret z jp continue_clear_screen; ;Fixed 6845 register values - taken from ;"IBM Monochrome Display and Printer Adapter" ;Hardware reference manual. init_data: .db 0,0,0,0,0ch,0bh,0dh,02h,19h,19h,06h,19h,0fh,52h,50h,61h ;Example text to be displayed test_string1: ;.db "--------------------------------------------------------------------------------" .db " * ,MMM8&&&. * " .db " MMMM88&&&&& . MDA/Herc. Demo for C-Z80 " .db " MMMM88&&&&&&& Computer. Full I/O " .db " * MMM88&&&&&&&& and video memory (32KB) " .db " MMM88&&&&&&&& access trough Z80 " .db " 'MMM88&&&&&&' I/O address space. " .db " 'MMM8&&&' * " .db " |\\___/| " .db " ) ( . . " .db " =\\ /= " .db " )===( * " .db " / \\ " .db " | | " .db " / \\ " .db " \\ / " .db " _/\\_/\\_/\\__ _/_/\\_/\\_/\\_/\\_/\\_/\\_/\\_/\\_/\\_ " .db " | | | |( ( | | | | | | | | | | " .db " | | | | ) ) | | | | | | | | | | " .db " | | | |(_( | | | | | | | | | | " .db " | | | | | | | | | | | | | | | " .db " jgs| | | | | | | | | | | | | | " .db " " .db " 8-bit ISA video card interface is a part of CP/M Compatibility Card for " .db " C-Z80 Computer. The card also implements cold/warm reset and 32/64KB RAM " .db " bankswitching circuits. (c) 2016 Michal Cierniak " .db 0 .END
Besides 8-bit ISA slot, I`ve also included two very important circuits on the board. One is Flash/ Extra RAM switching circuit which can replace the 32KB Flash ROM with an additional RAM chip of the same size uppon request – a single I/O write operation to ffffh port toggles the RS flip flop and the actual chip switching occurs (just like in Grant Searle`s design). The second added circuit is a cold/warm reset circuit, which gives a choice of resetting the whole system, or just the CPU – pressing RESET button resets the whole system, and enables Flash ROM. Pressing it with RESTORE button down resets only the CPU. These circuits required few small modifications to the existing hardware:
- RESET line had to be split into two parts – CPU and system reset. Reset circuit with CPU RESET signals are routed to new board.
- The “ROMSEL” signal on the mainboard had to be routed to new board instead of the FLASH ROM chip directly.
- Two new signals are introduced: Flash /CS and ExtRAM /CS – one for selecting Flash chip, and one for selecting extra 32KB static RAM chip.
- Previously unused RESTORE button on the keyboard is now pulled up to +5V and used for warm reset together with regular RESET button.
- I/O write signal for addres ffffh is taken from universal output port on the motherboard and routed to new add-on board (the original port function can still be used though – the bankswitching operation is meant to be one-time action only).
The schematics, board layout and pictures of the card itself:
Those new features are aimed to give my C-Z80 Computer full CP/M hardware compatibility. Below is an example program, that I`ve used to test the reset and bankswitching circuits. It copies the first 8KB of Flash contents into upper RAM area, preforms bankswitch, copies the 8KB code back to 0000h (which is now RAM area) and jumps to that address – the system is reinitialized but now ROM monitor is running in RAM, and all memory address space is in RAM. This can be checked by performing any write / read operation to first half of the memory space.
; Swaps FLASH with RAM ; Copies operating system from FLASH to RAM. .org 0d000h start: ld bc,0000h ld de,0a000h ;copying 8KB from flash 0000h to RAM at a000h loop: ld a,(bc) ld (de),a inc bc inc de ld a,020h cp b jp nz,loop ;swapping ram with rom ld a,0ffh ld bc,0ffffh out (c),a ;copying from RAM at a000h to RAM at 0000h ld bc,0a000h ld de,0000h loop2: ld a,(bc) ld (de),a inc bc inc de ld a,020h cp d jp nz,loop2 ;jump to RAM at 0000h jp 0000 .END
Some pictures of the installed card in the system:
The whole system is now ready for CP/M. I`m going to do some research about it, and implement it in near future. Before this, I`m going to do some experiments with the video card itself – try the Hercules and CGA modes.